1. Field of Invention
The present invention relates to a three-dimensional memory structure and manufacturing method thereof. More particularly, the present invention relates to a vertically stacked three-dimensional memory array and manufacturing method thereof.
2. Description of Related Art
Due to the rapid development of integrated circuit technologies, each integrated circuit contains an increasing number of electronic devices. Memory is a common semiconductor device most often used inside a personal computer and some electronic equipment. Earlier, each memory includes an array of memory cells on a single layer over a semiconductor substrate. The cross over area between each column and row constitutes a specified memory cell address. In general, memory cells within the same column or the same row have a common conductive wire connection. With this design, the only way to increase the level of integration is to reduce the size of each memory cell. A vertical stacked non-volatile memory structure is disclosed in U.S. Pat. No. 6,351,406. The method includes forming a three-dimensional multi-layered array memory structure over a substrate with each array layer having a plurality of memory cells such that the memory cells in the same column or row are connected to a common conductive wire.
FIG. 1 is a front view of a conventional three-dimensional multi-layered memory array structure. As shown in FIG. 1, if a first patterned conductive layer 1 lies in an east/west direction and a second patterned conductive layer 3 lies in a south/north direction above the first patterned conductive layer 1, a cylindrical memory cell 5 is formed in the area of intersection between the vertical projection of the second patterned conductive layer 3 and the first patterned conductive layer 1. Furthermore, if a third patterned conductive layer 7 lies in an east/west direction, a cylindrical memory cell 9 is formed in the area of intersection between the vertical projection of the third patterned conductive layer 7 and the second patterned conductive layer 3. In other words, according to the aforementioned stacking method, even-numbered patterned conductive layers lie in a south/north direction and odd-numbered patterned conductive layers lie in an east/west direction.
Although U.S. Pat. No. 6,351,406 has proposed a method of manufacturing a vertical stacked non-volatile memory for increasing overall level of device integration, the method requires N+1 photolithographic processes to form the N memory cell array layers over a substrate. Along with the photolithographic steps needed to producing interconnecting vias, the total number of processing steps is exceptionally high. In other words, the stacked three-dimensional memory is rather difficult and costly to manufacture.